For both IC debug and failure analysis, a goal is to understand a root cause of a failure. For debug analysis, the root-cause information can be provided to the design engineers who make appropriate changes to the mask set. In failure analysis, the data can be provided to the IC fabrication facility to effect changes directed toward improving yield and/or reliability. In either case, scan-based electrical test is usually the first tool used to diagnose a problem. Automatic test pattern generation (ATPG) can be used to sensitize defects in order to localize them. In many cases, the diagnostic information returned from such ATPG tests is inconclusive in localizing a problem, so that further, more refined testing by the physical probing of the signals on an IC chip is indicated. As will be discussed below, electrical design-for-test (DFT) features such as a scan-based architecture will partially localize a problem but even when supplemented by diagnostic programs can be insufficient for complete localization.
Scan testing is usually for digital circuitry made up of blocks of combinatorial logic alternating with registers made up of latches that store logical states (0's and 1's are represented by corresponding ranges of voltage levels). This is sometimes referred to as a register-transfer description. Signals propagate from one register to a next register through a block of combinatorial logic, with the register to register transfer being timed by a clock pulse. In between clock pulses, the latches retain logic states. Registers, and corresponding latches, that accept input logic states for a block of digital circuitry can be “source registers” and “source latches,” respectively. Electrical testing involves testing logic circuitry by applying a set of logical 0's and 1's to a set of source latches, and observing the resulting logical 0's and 1's at a set of sink latches. A sequence of ordered sets of such logical inputs is often referred to as a test vector. Sink latches can be observed after one or more clock pulses. As digital IC integration levels increase, it is often desirable to be able to test individual sub-blocks of digital circuitry on an IC that are not directly accessible by the IC's operational input and output ports. Boundary-scan methods can overcome this problem by surrounding inputs and outputs of a digital circuit sub-block to be tested with a boundary-scan shift register as illustrated by the example shown in FIG. 1. Boundary-scan testing involves serially loading a set of inputs through a serial input port 403 into that part of the boundary-scan register that is configured for connection to the inputs of the circuit block to be tested, designated as 405 in FIG. 1. These inputs are then clocked through the circuitry to be tested 405, and the corresponding outputs are captured in that part of the boundary-scan shift register that is configured to be connected to circuitry outputs 402B. Subsequently, the captured outputs can be clocked out of the boundary-scan register and serially read at serial output port 404. Circuitry inputs and outputs are usually configured with multiplexers (electronic two-to-one selector switches, not shown) so that they can be connected with a boundary scan register in an IC test mode, and connected with the other IC logic circuitry in an operational IC mode. Often the boundary scan register consists of latches that normally operate as parallel registers when the IC is in service mode, along with associated logic so that they can function as serially connected latches in boundary-scan test mode. Often the clock input to the circuit to be tested is preempted by an external tester in test mode, in order to coordinate the timing of the boundary-scan register logic-state loading and unloading for the logic sub-block to be tested.
Physical IC testing is distinguished from electrical IC testing in that it does not make use of operational IC outputs, or boundary-scan outputs. Physical IC testing directly measures electrical waveforms at nodes within the IC, or measures other physical manifestations such as electromagnetic radiation to infer electrical waveforms, typically in response to test vectors provided at an IC's operational and/or boundary-scan inputs.
There are several methods of probing on-die electrical waveforms, including: (i) direct electrical/mechanical probing; (ii) electron-beam probing; and (iii) optical probing. The direct mechanical probing of on-die electrical signals, performed by placing very sharp probe tips on the nodes of interest, is sometimes impossibly difficult. Often, such nodes are designed to drive capacitive loads on the IC of a few 10 s of fF and would be unacceptably loaded by the capacitance of electrical probes, thereby perturbing circuit functioning. Node access can also present problems due to the large numbers of metal layers, and to the extremely small size of the nodes of interest on typical ICs. Flip-chip packaging only compounds the access problem. Electron-beam probing has historically been used, but it suffers from the same problems of access as do mechanical probes. Other techniques such as SQUID microscopy can have niche applications as well. Physical IC testing is typically used after initial electrical testing. This is because, compared to electrical testing, physical testing tends to be more expensive in terms of testing time and testing equipment. An engineer might be able to explore only one or a few test hypotheses per day using physical testing, whereas dozens could be explored in the same time via electrical testing, and so it is useful to rule out false hypotheses by electrical testing, where possible.
Optical probing is a common technique for the physical fault isolation and debug of integrated circuits. According to some techniques, the device-under-test (DUT) is put into a repetitive test loop, while data such as voltage waveforms for a node of interest, are collected non-invasively through the backside of the silicon IC die. A performance-limiting factor in optical probing can be often the long averaging time required to accumulate enough test data. This averaging time is directly proportional to the length of the test pattern (number of vectors and clock period). Thus, significantly shortening the test loop can greatly improve the performance of IC test systems using optical probing. For optical probing, the number of “care-bits” (i.e. bit sequences that diagnostically exercise a sink node of interest (i.e. a sink node whose logical state may indicate a performance fault for the digital circuitry under test) is usually quite small, on the order of a few 10 s of test vectors. For physical IC testing, any logic device having transistors switchable between logic states (a “node”) can be observed. The terms “sink latch” and “sink node” will be used interchangeably in the context of physical IC testing. FIG. 2 illustrates a sink node 201 in a digital circuit sub-block 200. By loading the scan chains with repetitions of these relatively few care-bits, one can dramatically reduce the time required to repetitively exercise the particular circuit node being probed.
Today, much optical probing is done through the back side of silicon ICs, using infrared light to which silicon is transparent, and viewing the transistors from “underneath.” Such techniques induce negligible loading on the circuitry under test and have test access to every transistor on a die, thus eliminating some roadblocks of the previously discussed probing techniques. A drawback of optical probing is that the signals acquired can be very weak. The low signal-to-noise ratio (SNR) requires the DUT to be put into a repetitive looping state; so that the optical signal can be averaged over very many such loops. A limitation, from a user's point of view, is the time it takes to acquire enough such “signal” to analyze functionality of the probed point, as this time usually limits the number of nodes that can be probed.
Time-resolved emission (TRE) data from optical probing can be acquired on commercially-available probing systems. This technique is non-invasive and can be used to collect high bandwidth signals (5 ps timing resolution is regularly obtained) through the back side of the silicon IC. TRE is based upon the observation that when a CMOS circuit switches, it can emit a faint pulse of light that can be detected and used to determine, with high accuracy, the time at which the circuit switched. The origin of this pulse of light is thought to be “hot” electrons and holes in the transistors, which emit blackbody radiation, as do hot ovens and the sun. These light pulses, which can be so faint as to require single-photon counting detection, can mark the rising and falling edges of a waveform.
Because these small light pulses mark signal waveforms, it is possible to acquire a waveform that represents the electrical waveform of the node, without an electrical contact between a probe and the node. However, a number of light pulses must be collected before such waveform can be accurately inferred.
A time to acquire the waveform, Tacq, depends on a number of parameters, as described by equation (1):
                                          T            acq                    =                                                                      T                  loop                                ⁡                                  [                                                            Δ                      ⁢                                                                                          ⁢                                              t                        jitter                                                                                    Δ                      ⁢                                                                                          ⁢                                              t                        res                                                                              ]                                            2                        ⁢                                          (                                                      R                    dark                                    ⁢                  Δ                  ⁢                                                                          ⁢                                      t                    jitter                                                  )                                            P                sig                2                                                    ,                            (        1        )            
Tloop is a loop length (typically 10 μs-1 ms) that described how often a care bit pattern is repeated; Δtjitter is a relative timing jitter of the detector (50 ps typ.) and the logic state transition time of a sink node of interest; Rdark is the dark count rate (30 KHz typ.); Psig is the expected number of photons within a peak per loop (10−3 to 10−6 typ.); and Δtres is a desired timing resolution, relating to how accurately a given waveform is to be determined (5-50 ps is typical). Given these numbers, the acquisition times typically can range from less than 1 second to about 40 hours, although typical acquisitions range from 2-20 minutes. Longer acquisition times are usually prohibitive, although there are a few accounts of 24-hour acquisitions.
According to equation (1), above, the acquisition time scales linearly with the loop length, so reducing the loop from the above-quoted 10 μs minimum to 100 ns, for instance, could yield a 100× improvement in acquisition times. So far, loop compression has typically not been applied, except in specialized cases when built-in self test (BIST) routines could be optimized, as in the case of memory circuits. Loop compression (described below) can allow better test efficiency and enable users to probe signals that otherwise would be too weak. Also,
      Δ    ⁢                  ⁢          t      jitter            Δ    ⁢                  ⁢          t      res      represents the signal to noise ratio (SNR), so that the SNR achieved during probing scales as the square root of the probing time. FIG. 3 presents experimentally measured data for an optically measured signal corresponding to logic state transitions for a repetitively excited circuit node, integrated for various test times. The improvement in measured signal amplitude and timing precision with increasing test time is evident.
The number of permutations for logic state values of a test vector can be very large, growing exponentially according to the number of source latches. LBIST generates a set of pseudo-random latch value patterns for the source latches. Expected values of sink latch logic values can be derived from a logic circuit description, corresponding to each particular set of source latch logic values. A digital circuit can then be tested with the sets of source latch logic states, typically by loading into a boundary-scan register, and the resulting sink latch logic states (typically after being read by off-loading a boundary scan register) can be compared with the expected logic states for the sink values. A discrepancy in test results and expected results indicates a performance fault for the digital circuit. Afterward a new set of pseudo-random latch values (test vector) can be loaded into the boundary-scan register and the process repeated. In some cases, sets of pseudo-random latch values with greater numbers of logical 1's or 0's, in order to more efficiently attempt to trigger sink node responses representing circuit performance faults.
One loop compression technique is described in U.S. Pat. No. 6,442,720 issued on Aug. 27, 2002 to Koprowski et al. (hereinafter “Koprowski”). According to Koprowski, sink nodes of interest can be identified by observing which sink nodes tend to fail. Test vectors corresponding to sink node failures are used to generate subsequent test vectors by appending a minimally time shifted (in terms of clock pulses) version of the original test vector to itself, such that the scan chain is loaded with interleaved versions of the test vector causing the sink node failure. Thus, the test vector compression scheme of Koprowski increases the number of times a given failure can be exercised, but the precise timing of when that failure can be exercised varies because the interleaving causes the triggering event to occur on irregular intervals (see FIG. 8 of Kaprowski). Referring to equation (1) this compression scheme reduces the value of Tloop, thereby proportionally reducing acquisition time, Tacq.
Regarding the detection of sink node logic state transitions by optical techniques, the number of photons per transistor per switching event decreases with each process generation in part due to shrinking transistor geometries and logic state noise margins, although the emission is predicted to be present in all process geometries for the foreseeable future. Left unchecked, this trend could result in unacceptably long acquisition times for testing.
As IC devices continue to scale, it will be useful to supplement improvements in TRE system performance by shortening the test loops being used. The benefits of loop compression should apply independently of any other voltage or other setup conditions. In cases where the acquisition time is already adequate, one can average the data for many more loops in the same acquisition time, yielding much better signal to noise ratios (SNR). This can allow the extraction of additional information that normally would require an impractically long time to acquire, such as rising edges due to rush-through current; waveforms from PMOS transistors; leakage; and glitches. Loop compression should also benefit other probing techniques such as laser voltage probing (LVP).
Additionally, it is desirable to be able to improve test instrument sensitivity by optimally synchronizing the optical sensing process with the timing of photon emissions. Tack of equation (1) is proportional to the cube of Tjitter, so reducing Tjitter in equation (1) is desirable.